Name
Title | ||
|---|---|---|
A 15 MHz – 600 MHz, 20 mW, 0.38 mm 2 , fast coarse locking digital DLL in 0.13μm CMOS |
Abstract | ||
|---|---|---|
A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a line linear loop achieves low jitter (8.9 ps rms @ 600 MHz) and tracks PVT variations. The DLL consumes 20 mW and occupies a 470 square m X 800 square m area in 0.13 mu m CMOS. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ESSCIRC.2008.4681799 | Proceedings of the European Solid-State Circuits Conference |
Keywords | DocType | ISSN |
jitter,digital control,low power electronics,delay lock loop,binary search | Conference | 1930-8833 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sebastian Hoyos | 1 | 234 | 29.24 |
| c w tsang | 2 | 0 | 0.34 |
| johan vanderhaegen | 3 | 0 | 0.34 |
| Yun Chiu | 4 | 241 | 32.85 |
| Yasutoshi Aibara | 5 | 2 | 1.14 |
| Haideh Khorramabadi | 6 | 0 | 0.68 |
| borivoje nikolic | 7 | 6 | 1.87 |