Name
Abstract | ||
|---|---|---|
Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. These techniques need to evolve with modern architectures supporting wide memory accesses. We investigate array interleaving, a data layout transformation technique that achieves energy efficiency by combining the storage of data elements from multiple arrays in contiguous locations, in an attempt to exploit spatial locality. The transformation reduces the number of memory accesses by loading the right set of data into vector registers, thereby minimizing redundant memory fetches. We perform a global analysis of array accesses, and account for possibly different array behavior in different loop nests that might ultimately lead to changes in data layout decisions for the same array across program regions. Our technique relies on detailed estimates of the savings due to interleaving, and also the cost of performing the actual data layout modifications. We also account for the vector register widths and the possibility of choosing the appropriate granularity for interleaving. Experiments on several benchmarks show a 6--34% reduction in memory energy due to the strategy. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2747875 | ACM Transactions on Design Automation of Electronic Systems |
Keywords | DocType | Volume |
Design,Data layout,memory energy optimization,SIMD architecture | Journal | 20 |
Issue | ISSN | Citations |
3 | 1084-4309 | 4 |
PageRank | References | Authors |
0.42 | 28 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Namita Sharma | 1 | 15 | 3.74 |
| Preeti Ranjan Panda | 2 | 786 | 89.40 |
| Francky Catthoor | 3 | 3932 | 423.30 |
| Praveen Raghavan | 4 | 308 | 47.48 |
| T. Vander Aa | 5 | 163 | 17.86 |