Title
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.
Abstract
This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA p...
Year
DOI
Venue
2016
10.1109/JSSC.2015.2510026
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Switches,Baseband,Radio frequency,Power generation,Gain,CMOS integrated circuits,Timing
Power gain,Electrical efficiency,Transmitter power output,Power semiconductor device,Computer science,Electronic engineering,Linear amplifier,RF power amplifier,Electrical engineering,Power bandwidth,Switched-mode power supply
Journal
Volume
Issue
ISSN
51
3
0018-9200
Citations 
PageRank 
References 
3
0.57
9
Authors
4
Name
Order
Citations
PageRank
Haoyu Qian141.30
Qiyuan Liu230.57
Jose Silva-Martinez363086.56
Sebastian Hoyos423429.24