Name
Abstract | ||
|---|---|---|
The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract the arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 Million gates. The procedure has linear runtime and memory complexity, measured by the number of logic gates. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2744769.2744925 | DAC |
Field | DocType | ISSN |
Arithmetic function,Boolean circuit,Functional verification,Pass transistor logic,Computer science,Arbitrary-precision arithmetic,Algorithm,Arithmetic logic unit,Electronic engineering,Saturation arithmetic,Arithmetic circuit complexity | Conference | 0738-100X |
Citations | PageRank | References |
24 | 1.03 | 16 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maciej J. Ciesielski | 1 | 629 | 74.80 |
| Cunxi Yu | 2 | 98 | 9.64 |
| Walter Brown | 3 | 47 | 3.10 |
| Duo Liu | 4 | 78 | 4.08 |
| André Rossi | 5 | 137 | 13.13 |