Name
Abstract | ||
|---|---|---|
Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel cells, providing useful methods to estimate area and wirelength. These methods can also be applied in series-parallel topologies. The experiments performed in this paper show an effectively optimization on non-series-parallel layouts. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2800986.2801008 | SBCCI |
Keywords | Field | DocType |
Placement, routing, non-series-parallel networks, physical synthesis, automatic layout generation | Logical topology,Logic gate,Computer science,Place and route,Electronic engineering,Network topology,Topology optimization,Series and parallel circuits,Physical synthesis,Transistor | Conference |
Citations | PageRank | References |
2 | 0.44 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maicon Schneider Cardoso | 1 | 3 | 2.17 |
| Leomar Soares da Rosa Jr. | 2 | 8 | 5.35 |
| Felipe de Souza Marques | 3 | 34 | 9.47 |