Leomar Soares da Rosa Jr. - Citegraph

Author Info

Name	Affiliation	Papers
LEOMAR SOARES DA ROSA JR.	Univ Fed Rio Grande do Sul, Inst Informat, Porto Alegre, RS, Brazil	15
Collaborators	Citations	PageRank
31	8	5.35
Referers	Referees	References
20	199	88

Search Limit

100199

Publications (15 rows)

Collaborators (31 rows)

Referers (20 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Straightforward Methodology for QCA Circuits Design	0	0.34	2020
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability	0	0.34	2020
An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing	0	0.34	2019
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates	0	0.34	2019
A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing	0	0.34	2018
Transistor placement strategies for non-series-parallel cells	0	0.34	2017
Transistor Count Optimization in IG FinFET Network Design.	0	0.34	2017
Physical design of supergate cells aiming geometrical optimizations	0	0.34	2016
Graph-Based Transistor Network Generation Method for Supergate Design	5	0.49	2016
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding	0	0.34	2016
Evaluating Geometric Aspects of Non-Series-Parallel Cells	2	0.44	2015
A new general purpose line probe routing algorithm.	0	0.34	2014
Exploring Independent Gates in FinFET-Based Transistor Network Generation	0	0.34	2014
SwitchCraft: a framework for transistor network design	1	0.36	2010
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering	0	0.34	2008

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