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FELIPE DE SOUZA MARQUES
Author Info
Open Visualization
Name
Affiliation
Papers
FELIPE DE SOUZA MARQUES
Nangate Inc, Santa Clara, CA USA
24
Collaborators
Citations
PageRank
35
34
9.47
Referers
Referees
References
84
282
163
Search Limit
100
282
Publications (24 rows)
Collaborators (35 rows)
Referers (84 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A Straightforward Methodology for QCA Circuits Design
0
0.34
2020
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling
0
0.34
2020
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability
0
0.34
2020
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing
1
0.36
2020
Libra: An Automatic Design Methodology for CMOS Complex Gates.
1
0.39
2018
Area-Aware Design of Static CMOS Complex Gates
0
0.34
2018
Post-Processing Of Supergate Networks Aiming Cell Layout Optimization
0
0.34
2017
Transistor placement strategies for non-series-parallel cells
0
0.34
2017
A Survey Of Path Search Algorithms For Vlsi Detailed Routing
1
0.36
2017
Transistor Count Optimization in IG FinFET Network Design.
0
0.34
2017
Physical design of supergate cells aiming geometrical optimizations
0
0.34
2016
Graph-Based Transistor Network Generation Method for Supergate Design
5
0.49
2016
Evaluating Geometric Aspects of Non-Series-Parallel Cells
2
0.44
2015
Exploring Independent Gates in FinFET-Based Transistor Network Generation
0
0.34
2014
Efficient transistor-level design of CMOS gates
1
0.36
2013
Improving the methodology to build non-series-parallel transistor arrangements
2
0.41
2013
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
2
0.41
2012
KL-cuts: a new approach for logic synthesis targeting multiple output blocks
4
0.50
2010
Improvements on the detection of false paths by using unateness and satisfiability
0
0.34
2010
SwitchCraft: a framework for transistor network design
1
0.36
2010
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
0
0.34
2008
A comparative study of CMOS gates with minimum transistor stacks
3
0.48
2007
Fast disjoint transistor networks from BDDs
6
0.62
2006
A new approach to the use of satisfiability in false path detection
5
0.58
2005
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