Title | ||
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Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology |
Abstract | ||
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This paper addresses the power reduction techniques for the ultra-low power integrated circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi-zero leakage consumption, almost instant back-up and wake-up time and will be robust to unstable supply environments. This paper presents the implementation of the non-volatile C-element and Half-Buffer, based on hybrid technology incorporating 28nm CMOS FD-SOI and 40nm STT-MRAM magnetic technologies. We discuss our recent simulation results of the proposed non-volatile blocks and as well more complex structures based on them. We derive the criteria of the implementation efficiency and compare the conventional asynchronous blocks with the proposed non-volatile ones. |
Year | DOI | Venue |
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2015 | 10.1109/ASYNC.2015.27 | 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems |
Keywords | Field | DocType |
size 28 nm,size 40 nm | Asynchronous communication,Leakage (electronics),CMOS,Electronic engineering,Non-volatile memory,Engineering,Transistor,Electronic circuit,Electrical engineering,Integrated injection logic,Low-power electronics | Conference |
ISSN | Citations | PageRank |
1522-8681 | 3 | 0.45 |
References | Authors | |
14 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Eldar Zianbetov | 1 | 33 | 7.71 |
Edith Beigne | 2 | 536 | 52.54 |
Gregory Di Pendina | 3 | 33 | 7.27 |