Name
Abstract | ||
|---|---|---|
It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in submicron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISVLSI.2015.67 | IEEE Computer Society Annual Symposium on VLSI |
Field | DocType | ISSN |
Stuck-at fault,Delay calculation,Logic gate,Radio frequency,Electronic engineering,Engineering,Electronic circuit,Electrical engineering,Fault indicator | Conference | 2159-3469 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Senling Wang | 2 | 18 | 5.91 |
| Hiroshi Takahashi | 3 | 148 | 24.32 |
| Shin-ya Kobayashi | 4 | 38 | 8.60 |
| Kewal K. Saluja | 5 | 1483 | 141.49 |