Name
Abstract | ||
|---|---|---|
The path delay fault model is effective in detecting small delay defects. The proposed approach identifies the delay behavior of paths in various circuit instances without enumerating them. It selects critical paths through path implicit operations on a compact data structure potentially containing an exponential number of path candidates. The experimental analysis on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed approach is highly scalable and effective. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ICCD.2015.7357174 | International Conference on Computer Design |
Field | DocType | Citations |
Delay calculation,Data structure,Monte Carlo method,Logic gate,Exponential function,Computer science,Real-time computing,Correlation,Fault model,Scalability | Conference | 1 |
PageRank | References | Authors |
0.35 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahish Mysore Somashekar | 1 | 7 | 1.90 |
| Spyros Tragoudas | 2 | 625 | 88.87 |
| R. Jayabharathi | 3 | 12 | 4.42 |