Paper Info
Title
A methodology for power characterization of associative memories
Abstract
Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.
Year
DOI
Venue
2015
10.1109/ICCD.2015.7357156
International Conference on Computer Design
Keywords
Field
DocType
Content addressable memory (CAM), power modeling, VLSI circuits, digital electronic circuits, NAND cell, NOR cell, Ternary cell, Pattern Recognition
Computer-aided manufacturing,Power analysis,Content-addressable memory,Computer science,Massively parallel,Parallel computing,Electronic engineering,Chip,Data type,Transistor,Computer hardware,Very-large-scale integration
Conference
Citations 
PageRank 
References 
2
0.41
6
Authors
8
Name
Order
Citations
PageRank
Dawei Li172.23
Siddhartha Joshi222.10
Seda Öǧrenci Memik348842.57
James Hoff421.09
Sergo Jindariani530.78
Tiehui Liu620.75
Jamieson Olsen720.75
Nhan Tran8186.08