Name
Title | ||
|---|---|---|
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology |
Abstract | ||
|---|---|---|
Voltage level converters are critical components in multi supply ultra-low voltage designs, especially when signals need to be converted from the sub-threshold to the above-threshold domain. In these designs, advanced technology processes, such as the Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI), are greatly desired since they intrinsically allow controlling the Drain Induced Barrier Lowering effect (DIBL) and the Gate Induced Drain Leakage (GIDL), in addition to the reduction of the effects of process variations. Moreover, these technologies provide a group of architectural and device-level techniques for threshold voltage adjustment that can be efficiently adopted to combine high performances and low energy consumption. However, specific design strategies should be applied to efficiently exploit all these potentialities. This paper investigates how the physical design of level converters can benefit from the synergistic adoption of the knobs available in the UTBB FDSOI technology (poly biasing, flip-well, single-well, back biasing). In particular, three mixed single well configurations have been implemented and analyzed. This research work demonstrates that the specific selected approach allows decreasing the energy per cycle consumption, the leakage current and the delay by up to 35.3%, 70.4%, and 6.2%, respectively, with respect to the basic conventional design strategy. Furthermore, statistical analysis confirmed that these advantages are maintained for a wide range of process variations, also improving the functional yield and the minimum input voltage causing the level converter failure. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ICCD.2015.7357157 | International Conference on Computer Design |
Keywords | Field | DocType |
Level Converter (LC),energy optimization,subthreshold,ultra-low power,UTBB | Leakage (electronics),Computer science,Voltage,CMOS,Electronic engineering,Subthreshold conduction,Physical design,Threshold voltage,Electrical engineering,Drain-induced barrier lowering,Biasing | Conference |
Citations | PageRank | References |
2 | 0.42 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pasquale Corsonello | 1 | 278 | 38.06 |
| Stefania Perri | 2 | 264 | 33.11 |
| Fabio Frustaci | 3 | 129 | 17.55 |