Paper Info
Title
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Abstract
A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty-cycle correction modes, CML-to-CMOS converters with wide range operation, active resonant loads at the end of WCK lane, and an on-chip de-emphasis circuit at a 4-to-1 multiplexer output as shown in Fig. 18.1.1. In addition, extra power pads improve the power distribution and release the frequency limitation at the memory core.
Year
Venue
Field
2016
ISSCC
Dram,Computer science,Multiplexer,Cmos process,Electronic engineering,Converters,Jitter,Temperature measurement,Electrical engineering
DocType
Citations 
PageRank 
Conference
1
0.48
References 
Authors
4
17
Name
Order
Citations
PageRank
Hye-Yoon Joo172.08
Seung-Jun Bae216732.40
Young-Soo Sohn311521.21
Young-Sik Kim439454.26
Kyung-Soo Ha5527.63
Min-Su Ahn621.91
Young-Ju Kim7112.30
Yong-Jun Kim811.16
Ju-Hwan Kim991.36
Won Jun Choi10143.58
Chang-Ho Shin11456.84
Soo Hwan Kim12168.11
Byeong-Cheol Kim13325.48
Seung-Bum Ko1410.48
Kwang-Il Park1516325.68
Seong-jin Jang169927.16
Gyo-Young Jin17165.43