Name
Abstract | ||
|---|---|---|
Prior works have demonstrated opportunities for achieving more minimized combinational circuits by introducing combinational loops during the synthesis. However, they achieved this by using a branch-and-bound technique to explore possible cyclic dependencies of circuits, which may not scale well for complex designs. Instead of using exploration, this paper proposes a formal algorithm using logic implication to identify cyclifiable structure candidates directly, or to create them aggressively in circuits. Additionally, we also propose a SAT-based algorithm to validate whether the formed loops are combinational or not. The effectiveness and scalability of the identification and validation algorithms are demonstrated in the experimental results performed on a set of IWLS 2005 benchmarks. As compared to the state-of-the-art algorithm, our validation algorithm produces speedups ranging from 2 to 2350 times. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/SOCC.2015.7406959 | 2015 28th IEEE International System-on-Chip Conference (SOCC) |
Keywords | Field | DocType |
IWLS 2005 benchmarks,SAT based algorithm,cyclifiable structure,branch-and-bound technique,combinational loops,cyclic combinational circuits | Sequential logic,Computer science,Theoretical computer science,Combinational logic,Ranging,Electronic circuit,Computer engineering,Scalability | Conference |
Citations | PageRank | References |
1 | 0.38 | 19 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jui-Hung Chen | 1 | 2 | 0.75 |
| Yung-Chih Chen | 2 | 413 | 39.89 |
| Wan-Chen Weng | 3 | 2 | 0.75 |
| Ching-Yi Huang | 4 | 58 | 10.06 |
| Wang Chun-Yao | 5 | 251 | 36.08 |