Name
Title | ||
|---|---|---|
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS |
Abstract | ||
|---|---|---|
A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<;10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858399 | VLSIC |
Field | DocType | Citations |
Shift register,Oversampling,Timing margin,Computer science,Injection locking,Electronic engineering,CMOS,Jitter,Distortion,Bit error rate | Conference | 2 |
PageRank | References | Authors |
0.41 | 4 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Li | 1 | 2 | 0.41 |
| Shuai Chen | 2 | 26 | 7.63 |
| Liqiong Yang | 3 | 9 | 2.15 |
| Rui Bai | 4 | 2 | 2.10 |
| Weiwu Hu | 5 | 364 | 33.31 |
| Freeman Y. Zhong | 6 | 42 | 3.75 |
| Samuel Palermo | 7 | 46 | 7.88 |
| Patrick Yin Chiang | 8 | 150 | 19.20 |