Title
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS
Abstract
This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1x at iso-area in 28nm FDSOI.
Year
Venue
Field
2015
Symposium on VLSI Circuits-Digest of Papers
Sense amplifier,Capacitor,Computer science,Exploit,Electronic engineering,CMOS,Redundancy (engineering),Transistor,Electrical engineering,Offset (computer science),Amplifier
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
0
5
Name
Order
Citations
PageRank
Mahmood Khayatzadeh1493.53
Fabio Frustaci212917.55
David Blaauw38916823.47
Dennis Sylvester45295535.53
Massimo Alioto570688.98