Name
Title | ||
|---|---|---|
A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement |
Abstract | ||
|---|---|---|
A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858446 | VLSIC |
Field | DocType | Citations |
Electrical efficiency,Phase-locked loop,Ring oscillator,Noise floor,Computer science,Phase noise,Electronic engineering,Jitter,Calibration free,CPU multiplier | Conference | 2 |
PageRank | References | Authors |
0.57 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Romesh Kumar Nandwana | 1 | 45 | 10.36 |
| Tejasvi Anand | 2 | 110 | 16.98 |
| Saurabh Saxena | 3 | 174 | 16.84 |
| Seong Joong Kim | 4 | 47 | 8.95 |
| Mrunmay Talegaonkar | 5 | 123 | 15.61 |
| Ahmed Elkholy | 6 | 77 | 16.19 |
| Woo-Seok Choi | 7 | 105 | 12.58 |
| Amr Elshazly | 8 | 242 | 28.08 |
| Pavan Kumar Hanumolu | 9 | 554 | 84.82 |