Name
Title | ||
|---|---|---|
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSIC.2012.6243830 | VLSIC |
Field | DocType | Citations |
Clock gating,Computer science,Clock domain crossing,Electronic engineering,Clock skew,Synchronous circuit,Digital clock manager,Jitter,CPU multiplier,Clock angle problem | Conference | 2 |
PageRank | References | Authors |
0.41 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiichi Niitsu | 1 | 126 | 38.14 |
| Naohiro Harigai | 2 | 6 | 2.58 |
| Daiki Hirabayashi | 3 | 3 | 1.47 |
| daiki oki | 4 | 2 | 0.75 |
| Masato Sakurai | 5 | 24 | 4.16 |
| Osamu Kobayashi | 6 | 18 | 4.56 |
| Takahiro J. Yamaguchi | 7 | 176 | 35.24 |
| haruo kobayashi | 8 | 4 | 1.17 |