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OSAMU KOBAYASHI
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Name
Affiliation
Papers
OSAMU KOBAYASHI
Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan 222-0033
8
Collaborators
Citations
PageRank
27
18
4.56
Referers
Referees
References
43
58
16
Publications (8 rows)
Collaborators (27 rows)
Referers (43 rows)
Referees (58 rows)
Title
Citations
PageRank
Year
Design And Theoretical Analysis Of A Clock Jitter Reduction Circuit Using Gated Phase Blending Between Self-Delayed Clock Edges
0
0.34
2019
A CMOS PWM Transceiver Using Self-Referenced Edge Detection
0
0.34
2015
Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques.
0
0.34
2015
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity
1
0.38
2013
Two-Tone Signal Generation For Adc Testing
2
0.53
2013
Two-Tone Signal Generation for Communication Application ADC Testing
5
0.78
2012
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges
2
0.41
2012
Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator.
8
1.45
2012
1