Name
Abstract | ||
|---|---|---|
A phase interpolator (PI) based fractional divider is used to improve the quantization noise shaping properties of a 1-bit ΔΣ frequency-to-digital converter (FDC). Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed FDC in place of a high resolution TDC and achieves -102dBc/Hz in-band phase noise and 852fsrms integrated jitter (1k-40M) while generating 5.054GHz output from 31.25MHz input. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/VLSIC.2014.6858392 | VLSIC |
Field | DocType | Citations |
Phase-locked loop,Computer science,Phase noise,Delta-sigma modulation,Cmos process,Modulation,Electronic engineering,Bandwidth (signal processing),Jitter,Quantization (signal processing),Electrical engineering | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mrunmay Talegaonkar | 1 | 123 | 15.61 |
| Tejasvi Anand | 2 | 110 | 16.98 |
| Ahmed Elkholy | 3 | 77 | 16.19 |
| Amr Elshazly | 4 | 242 | 28.08 |
| Romesh Kumar Nandwana | 5 | 45 | 10.36 |
| Saurabh Saxena | 6 | 174 | 16.84 |
| Brian Young | 7 | 118 | 12.20 |
| Woo-Seok Choi | 8 | 105 | 12.58 |
| Pavan Kumar Hanumolu | 9 | 554 | 84.82 |