Name
Title | ||
|---|---|---|
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. |
Abstract | ||
|---|---|---|
Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Re... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TVLSI.2015.2506780 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Logic gates,Fabrics,Boolean functions,Data structures,Nanoscale devices,Tunneling,Single electron transistors | Boolean function,Data structure,Logic gate,Coulomb blockade,Computer science,Electronic engineering,Minification,Mapping algorithm,Transistor,Nanowire | Journal |
Volume | Issue | ISSN |
24 | 6 | 1063-8210 |
Citations | PageRank | References |
3 | 0.39 | 12 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yi Huang | 1 | 58 | 10.06 |
| Yun-Jui Li | 2 | 4 | 0.75 |
| Chian-Wei Liu | 3 | 12 | 1.34 |
| Wang Chun-Yao | 4 | 251 | 36.08 |
| Yung-Chih Chen | 5 | 413 | 39.89 |
| Suman Datta | 6 | 415 | 51.93 |
| Narayanan Vijaykrishnan | 7 | 6955 | 524.60 |