Name
Abstract | ||
|---|---|---|
Increasing fault rates in current and future technology nodes coupled with on-chip components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) designs. Given the central role of NoCs in today’s many-core chips, permanent faults impeding their original functionality may significantly influence performance, energy consumption, and correct operation of the entire system. As a result, fault-tolerant NoC design gained much attention in recent years. In this article, we review the vast research efforts regarding a NoC’s components, namely, topology, routing algorithm, router microarchitecture, as well as system-level approaches combined with reconfiguration; discuss the proposed architectures; and identify outstanding research questions. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2886781 | ACM Comput. Surv. |
Keywords | Field | DocType |
Permanent failures,topology,routing algorithms,router microarchitecture,system-level redundancy,reconfiguration | Computer science,Router microarchitecture,Energy consumption,Control reconfiguration,Embedded system,Routing algorithm | Journal |
Volume | Issue | ISSN |
48 | 4 | 0360-0300 |
Citations | PageRank | References |
10 | 0.46 | 85 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sebastian Werner | 1 | 11 | 0.83 |
| Javier Navaridas | 2 | 201 | 23.58 |
| Mikel Luján | 3 | 540 | 46.40 |