Name
Title | ||
|---|---|---|
A 28-Nm 484-Fj/Writecycle 650-Fj/Readcycle 8t Three-Port Fd-Soi Sram For Image Processor |
Abstract | ||
|---|---|---|
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140 ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55 ns (= 18.2 MHz), at which 484 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1587/transele.E99.C.901 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
image memory, multi-port SRAM, 8T, FD-SOI, 28-nm, majority logic | Majority logic,Silicon on insulator,Static random-access memory,Electronic engineering,Image processor,Engineering | Journal |
Volume | Issue | ISSN |
E99C | 8 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haruki Mori | 1 | 0 | 1.35 |
| Yohei Umeki | 2 | 2 | 1.72 |
| Shusuke Yoshimoto | 3 | 30 | 12.56 |
| Shintaro Izumi | 4 | 82 | 31.56 |
| Koji Nii | 5 | 223 | 44.78 |
| Hiroshi Kawaguchi | 6 | 37 | 21.08 |
| masahiko yoshimoto | 7 | 117 | 34.06 |