Name
Title | ||
|---|---|---|
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. |
Abstract | ||
|---|---|---|
A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key features and considerations of the proposed architecture are described. A proof-of-concept 16 lane, 16 Gb/s per lane source-synchronous I/O test chip was designed and fabricated in a 32 nm SOI CMOS technology. Several circuit techniques emp... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/JSSC.2016.2550499 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Receivers,Clocks,Calibration,Redundancy,Timing,Integrated circuit interconnections,Equalizers | Electrical efficiency,Timing margin,Computer science,Communication channel,Electronic engineering,Chip,Serializer,Redundancy (engineering),Source-synchronous,Parallel port | Journal |
Volume | Issue | ISSN |
51 | 8 | 0018-9200 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Timothy O. Dickson | 1 | 141 | 22.86 |
| Yong Liu | 2 | 7 | 1.53 |
| Ankur Agrawal | 3 | 314 | 22.16 |
| John F. Bulzacchelli | 4 | 281 | 42.62 |
| Herschel A. Ainspan | 5 | 157 | 25.23 |
| Zeynep Toprak Deniz | 6 | 90 | 11.02 |
| Benjamin D. Parker | 7 | 87 | 12.51 |
| Michael P. Beakes | 8 | 215 | 21.36 |
| Mounir Meghelli | 9 | 78 | 14.76 |
| Daniel J. Friedman | 10 | 291 | 48.52 |