Paper Info
Title
Enabling The Heterogeneous Accelerator Model On Ultra-Low Power Microcontroller Platforms
Abstract
The stringent power constraints of complex microcontroller based devices (e.g. smart sensors for the IoT) represent an obstacle to the introduction of sophisticated functionality. Programmable accelerators would be extremely beneficial to provide the flexibility and energy efficiency required by fast-evolving IoT applications; however, the integration complexity and sub-10mW power budgets have been considered insurmountable obstacles so far. In this paper we demonstrate the feasibility of coupling a low power microcontroller unit (MCU) with a heterogeneous programmable accelerator for speeding-up computation-intensive algorithms at an ultra-low power (ULP) sub-10mW budget. Specifically, we develop a heterogeneous architecture coupling a Cortex-M series MCU with PULP, a programmable accelerator for ULP parallel computing. Complex functionality is enabled by the support for offloading parallel computational kernels from the MCU to the accelerator using the OpenMP programming model. We prototype this platform using a STM Nucleo board and a PULP FPGA emulator. We show that our methodology can deliver up to 60x gains in performance and energy efficiency on a diverse set of applications, opening the way for a new class of ULP heterogeneous architectures.
Year
Venue
Field
2016
PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
Kernel (linear algebra),Obstacle,Coupling,Programming paradigm,Efficient energy use,Computer science,Field-programmable gate array,Real-time computing,Microcontroller,Benchmark (computing),Embedded system
DocType
ISSN
Citations 
Conference
1530-1591
3
PageRank 
References 
Authors
0.38
15
5
Name
Order
Citations
PageRank
Francesco Conti 0001112518.24
Daniele Palossi2416.12
Andrea Marongiu333739.19
Davide Rossi441647.47
Luca Benini5131161188.49