Name
Title | ||
|---|---|---|
Efficient Fpga Acceleration Of Convolutional Neural Networks Using Logical-3d Compute Array |
Abstract | ||
|---|---|---|
Convolutional Deep Neural Networks (DNNs) are reported to show outstanding recognition performance in many image-related machine learning tasks. DNNs have a very high computational requirement, making accelerators a very attractive option. These DNNs have many convolutional layers with different parameters in terms of input/output/kernel sizes as well as input stride. Design constraints usually require a single design for all layers of a given DNN. Thus a key challenge is how to design a common architecture that can perform well for all convolutional layers of a DNN, which can be quite diverse and complex. In this paper we present a flexible yet highly efficient 3D neuron array architecture that is a natural fit for convolutional layers. We also present our technique to optimize its parameters including onchip buffer sizes for a given set of resource constraint for modern FPGAs. Our experimental results targeting a Virtex-7 FPGA demonstrate that our proposed technique can generate DNN accelerators that can outperform the state-of-the-art solutions, by 22% for 32-bit floating-point MAC implementations, and are far more scalable in terms of compute resources and DNN size. |
Year | Venue | Field |
|---|---|---|
2016 | PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Kernel (linear algebra),Digital signal processing,Design for All,System on a chip,Convolutional neural network,Computer science,Field-programmable gate array,Real-time computing,Acceleration,Scalability |
DocType | ISSN | Citations |
Conference | 1530-1591 | 18 |
PageRank | References | Authors |
1.00 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Atul Rahman | 1 | 18 | 1.33 |
| Jongeun Lee | 2 | 429 | 33.71 |
| Kiyoung Choi | 3 | 1866 | 171.98 |