Name
Title | ||
|---|---|---|
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique |
Abstract | ||
|---|---|---|
To measure the variation of device V
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requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V
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for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V
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based on only the combined I
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measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of V
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mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of I
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measurement per DUT. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VTS.2016.7477268 | 2016 IEEE 34th VLSI Test Symposium (VTS) |
Keywords | Field | DocType |
WAT test structures,wafer acceptance test,model-based random forest,core model-fitting technique,parallel connected DUTs,SPICE simulation,binary search,nMOS transistors | ID measurement,Logic gate,Computer science,Simulation,Spice,Algorithm,Electronic engineering,Binary search algorithm,Random forest,Speedup | Conference |
ISSN | Citations | PageRank |
1093-0167 | 1 | 0.40 |
References | Authors | |
4 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-Ying Tsai | 1 | 1 | 0.73 |
| Kao-Chi Lee | 2 | 1 | 0.73 |
| Chien-Hsueh Lin | 3 | 1 | 0.73 |
| Sung-Chu Yu | 4 | 1 | 0.40 |
| Wen-Rong Liau | 5 | 1 | 0.40 |
| Alex Chun-Liang Hou | 6 | 1 | 0.40 |
| Ying-Yen Chen | 7 | 1 | 0.73 |
| Chun-Yi Kuo | 8 | 5 | 1.14 |
| Jih-Nung Lee | 9 | 1 | 0.40 |
| Mango C.-T. Chao | 10 | 48 | 7.38 |