Name
Title | ||
|---|---|---|
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. |
Abstract | ||
|---|---|---|
This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range o... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCSI.2016.2578960 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Jitter,Receivers,Timing,Clocks,Bandwidth,Detectors,Transceivers | Efficient energy use,Delay-locked loop,Electronic engineering,CMOS,Data rate,Jitter,Mathematics | Journal |
Volume | Issue | ISSN |
63 | 9 | 1549-8328 |
Citations | PageRank | References |
2 | 0.39 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Woo-Rham Bae | 1 | 40 | 14.93 |
| Gyu-Seob Jeong | 2 | 21 | 9.00 |
| Kwanseo Park | 3 | 22 | 9.60 |
| Sung-Yong Cho | 4 | 21 | 4.41 |
| Yoonsoo Kim | 5 | 129 | 19.27 |
| Deog-Kyoon Jeong | 6 | 626 | 119.05 |