Name
Abstract | ||
|---|---|---|
Relative Timing uses path based timing constraints to guarantee that a circuit conforms to its behavioral specification. Timing constraints are used to order signal transitions or events in a circuit through corresponding minimum and maximum delay timing constraints. A circuit may have multiple sets of constraints, each of which, when satisfied, can individually ensure functional correctness. This paper presents a framework to evaluate and rank relative timing constraint sets for a given circuit. The constraint sets are evaluated on the basis of robustness of the constraints and conflicts between constraints in the same set. The analysis is automated by building a tool. The paper applies the methodology and tool to optimize the extraction of relative timing constraints for delay insensitive timing models of asynchronous circuits. This is demonstrated using a burst-mode controller. The optimization leads to an average tool runtime reduction of 94%. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASYNC.2016.23 | 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) |
Keywords | Field | DocType |
relative timing,bundled data,timing constraints,timing conflicts | Delay calculation,Asynchronous communication,Control theory,Computer science,Control theory,Correctness,Robustness (computer science),Static timing analysis,Electronic circuit | Conference |
ISSN | ISBN | Citations |
1522-8681 | 978-1-4673-9008-8 | 3 |
PageRank | References | Authors |
0.39 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jotham Vaddaboina Manoranjan | 1 | 3 | 1.07 |
| Kenneth S. Stevens | 2 | 185 | 25.65 |