Name
Abstract | ||
|---|---|---|
An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(2(4))(2) composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V. |
Year | Venue | Field |
|---|---|---|
2016 | Symposium on VLSI Circuits-Digest of Papers | Glitch,Key storage,Computer science,Efficient energy use,Internet of Things,Electronic engineering,CMOS,Hardware acceleration,Throughput,AES implementations,Embedded system |
DocType | Citations | PageRank |
Conference | 2 | 0.41 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yiqun Zhang | 1 | 78 | 6.33 |
| Kuiyuan Yang | 2 | 148 | 20.89 |
| Mehdi Saligane | 3 | 47 | 6.01 |
| David Blaauw | 4 | 8916 | 823.47 |
| Dennis Sylvester | 5 | 5295 | 535.53 |