Name
Abstract | ||
|---|---|---|
A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal ti... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/JSSC.2016.2604297 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Capacitance,Computer architecture,Loading,Calibration,Performance evaluation,Timing,Resistance | Journal | 52 |
Issue | ISSN | Citations |
1 | 0018-9200 | 6 |
PageRank | References | Authors |
0.51 | 0 | 29 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dongku Kang | 1 | 28 | 6.80 |
| Woopyo Jeong | 2 | 129 | 14.49 |
| Chulbum Kim | 3 | 26 | 2.15 |
| Doo-Hyun Kim | 4 | 155 | 33.21 |
| Yong-Sung Cho | 5 | 40 | 4.95 |
| Kyung-Tae Kang | 6 | 33 | 3.61 |
| Jinho Ryu | 7 | 80 | 7.73 |
| Kyungmin Kang | 8 | 51 | 7.13 |
| Sungyeon Lee | 9 | 23 | 2.43 |
| Wandong Kim | 10 | 23 | 2.77 |
| Hanjun Lee | 11 | 23 | 2.77 |
| Jaedoeg Yu | 12 | 41 | 3.91 |
| Nayoung Choi | 13 | 41 | 4.24 |
| Dong-Su Jang | 14 | 34 | 5.09 |
| Cheon An Lee | 15 | 6 | 0.85 |
| Young-Sun Min | 16 | 41 | 4.50 |
| Moosung Kim | 17 | 60 | 7.39 |
| An-Soo Park | 18 | 6 | 0.51 |
| Jae-Ick Son | 19 | 23 | 2.77 |
| In-Mo Kim | 20 | 6 | 0.51 |
| Ki Tae Park | 21 | 24 | 6.23 |
| Bong-Kil Jung | 22 | 23 | 2.77 |
| Doo-Sub Lee | 23 | 6 | 0.51 |
| Hyunggon Kim | 24 | 15 | 1.07 |
| Jeong-Don Ihm | 25 | 15 | 1.07 |
| Dae-Seok Byeon | 26 | 78 | 11.94 |
| Jin-Yup Lee | 27 | 6 | 0.51 |
| Ki-Tae Park | 28 | 197 | 19.35 |
| Kye-Hyun Kyung | 29 | 6 | 0.51 |