Name
Abstract | ||
|---|---|---|
Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2639533 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
Logic gates,Image edge detection,Detectors,Tunneling,Fabrics,Computer architecture,Computer science | Boolean function,Central processing unit,Logic gate,Coulomb blockade,CPU time,Computer science,Electronic engineering,Time limit,Transistor,Detector | Journal |
Volume | Issue | ISSN |
PP | 99 | 1063-8210 |
Citations | PageRank | References |
1 | 0.36 | 16 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yun-Jui Li | 1 | 4 | 0.75 |
| Ching-Yi Huang | 2 | 58 | 10.06 |
| Chia-Cheng Wu | 3 | 3 | 3.16 |
| Yung-Chih Chen | 4 | 413 | 39.89 |
| Wang Chun-Yao | 5 | 251 | 36.08 |
| Suman Datta | 6 | 23 | 3.77 |
| Vijay K. Narayanan | 7 | 138 | 10.99 |