Paper Info
Title
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis.
Abstract
High-level synthesis (HLS) enables designing at a higher level of abstraction to effectively cope with design complexity of emerging applications on modern programmable system-on-chip (SoC). While HLS continues to evolve with a growing set of algorithms, methodologies, and tools to efficiently map software designs onto optimized hardware architectures, there continues to lack realistic benchmark applications with sufficient complexity and enforceable constraints. In this paper we present a case study of accelerating face detection based on the Viola Jones algorithm on a programmable SoC using a C-based HLS flow. We also share our insights in porting a software-based design into a synthesizable implementation with HLS-specific data structures and optimizations. Our design is able to achieve a frame rate of 30 frames per second which is suitable for realtime applications. Our performance and quality of results are comparable to those of many traditional RTL implementations.
Year
DOI
Venue
2017
10.1145/3020078.3021753
FPGA
Field
DocType
Citations 
Computer science,Implementation,Real-time computing,Software,Face detection,Data structure,Computer architecture,Parallel computing,High-level synthesis,Field-programmable gate array,Frame rate,Porting,Embedded system
Conference
6
PageRank 
References 
Authors
0.45
9
4
Name
Order
Citations
PageRank
Nitish Kumar Srivastava1161.55
Steve Dai210410.71
Rajit Manohar3103896.72
Zhiru Zhang4102071.74