Paper Info
Title
Simulation-enabled development lot journey smoothening in a fully-utilised semiconductor manufacturing line.
Abstract
Technology and product development have high priority in an advanced semiconductor manufacturing facility such as the Infineon Dresden fab. From the perspective of line performance this means that short cycle times for development lots have to be guaranteed to enable the required learning cycles. Long-term simulation is used in dynamic capacity planning to find a compromise between short cycle times for the development corridor and high utilisation of the installed tool capacity. All products in the fab run with customer-specific due dates. As such, negative side-effects caused by the accelerated development lot corridor through increased dispatch priorities have to be minimised. In turn, for day-to-day operations short-term simulation is used for early detection of bottleneck situations and other sudden resource availability problems. With focus on the development corridor, a Lot Cycle Time Forecaster was realised. The aforementioned manifold applications of discrete-event simulation are described in this paper in more detail.
Year
DOI
Venue
2016
10.1109/WSC.2016.7822294
Winter Simulation Conference
Field
DocType
ISSN
Early detection,Bottleneck,Development Lot,Simulation,Semiconductor device modeling,Computer science,Semiconductor device fabrication,Capacity planning,New product development
Conference
0891-7736
ISBN
Citations 
PageRank 
978-1-5090-4484-9
0
0.34
References 
Authors
0
6
Name
Order
Citations
PageRank
Wolfgang Scholl1628.06
Matthias Förster200.34
Patrick Preuss3124.16
André Naumann401.69
Boon Ping Gan532934.25
Peter Lendermann621925.96