Name
Abstract | ||
|---|---|---|
This paper presents an FPGA architecture capable of implementing relative timing based asynchronous designs. Modifications are made to a traditional synchronous FPGA architecture to make it asynchronous capable, while retaining its capability as a fully functional synchronous FPGA. Such a design permits multi-frequency implementations. A test FPGA fabric is developed and evaluated with the implementation of a MIPS processor. The asynchronous MIPS processor implemented on the designed FPGA provides a performance improvement of 1.7× while also providing a power improvement of 2.3× compared to the synchronous version of the MIPS implemented on a counterpart synchronous FPGA. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSI-SoC.2016.7753538 | 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
field programmable gate arrays,multifrequency FPGA,asynchronous designs,synchronous FPGA architecture,test FPGA fabric,asynchronous MIPS processor | Asynchronous communication,Computer science,Field-programmable gate array,FPGA prototype,Implementation,Fpga architecture,Embedded system,Performance improvement | Conference |
ISBN | Citations | PageRank |
978-1-5090-3562-5 | 0 | 0.34 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jotham Vaddaboina Manoranjan | 1 | 3 | 1.07 |
| Solomon Surya Tej Mano Sajjan | 2 | 0 | 0.34 |
| Vivek B. Gujari | 3 | 0 | 0.34 |
| Kenneth S. Stevens | 4 | 185 | 25.65 |