Name
Abstract | ||
|---|---|---|
Scan-based tests may lead to overtesting of delay faults by bringing a circuit to states that the circuit cannot enter during functional operation. Functional broadside tests address this issue by using reachable states as scan-in states. Different strategies for generating functional broadside tests have been studied and implemented by academic tools. The main challenge that these procedures address is the identification of reachable states that are useful as scan-in states. This paper describes the generation of functional broadside tests using a commercial test generation tool. Our results demonstrate that it is possible to generate functional broadside tests without requiring any modifications to the commercial tool, and using the tests that the tool produces to obtain reachable states. This is expected to enable the generation of functional broadside tests for state-of-the-art designs that cannot be handled by academic tools. To demonstrate this point, we apply the procedure to two large logic blocks of the OpenSPARC T1 microprocessor. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISVLSI.2017.61 | 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
broadside tests,functional broadside tests,scan circuits,transition faults | Automatic test pattern generation,Broadside,Microprocessor,Electronic engineering,OpenSPARC,Engineering,Computer engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-6763-3 | 0 | 0.34 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naixing Wang | 1 | 0 | 1.69 |
| Bo Yao | 2 | 0 | 0.68 |
| Xijiang Lin | 3 | 687 | 42.03 |
| Irith Pomeranz | 4 | 3829 | 336.84 |