Name
Abstract | ||
|---|---|---|
Recently, methods for switch network generation have gain relevance. The main goal of these techniques is to minimize the number of transistors in the logical arrangement. However, theses methods do not consider optimizations at layout level. In this paper, we propose a post-processing technique in a state-of-art method for network generation to improve some layout aspects such as area, delay, power and parasitic capacitance. Experiments performed over a well-known benchmark demonstrate that the proposed technique allows average gains of 7.48% and 8.48% in the cell area and wirelength, respectively. Electrical characterization results have also shown improvements for propagation delay, transition delay, leakage and switching power in 4.18%, 4.94%, 7.52% and 12.40%, in that order. |
Year | Venue | Keywords |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | layout optimization, switches network, Kernel Finder post-processing |
Field | DocType | ISSN |
Kernel (linear algebra),Network generation,Parasitic capacitance,Propagation delay,Leakage (electronics),Computer science,Electronic engineering,Network switch,Switching power,Transistor,Electrical engineering | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gustavo H. Smaniotto | 1 | 0 | 0.34 |
| Regis Zanandrea | 2 | 0 | 0.68 |
| Maicon Schneider Cardoso | 3 | 3 | 2.17 |
| Renato Souza de Souza | 4 | 0 | 0.68 |
| Matheus T. Moreira | 5 | 104 | 19.98 |
| Felipe de Souza Marques | 6 | 34 | 9.47 |
| Leomar S. da Rosa Jr. | 7 | 25 | 4.75 |