Name
Abstract | ||
|---|---|---|
Various error models are being used in simulation of voltage-scaled arithmetic units to examine application-level tolerance of timing violations. The selection of an error model needs further consideration, as differences in error models drastically affect the performance of the application. Specifically, floating point arithmetic units (FPUs) have architectural characteristics that characterize its behavior. We examine the architecture of FPUs and design a new error model, which we call Critical Bit. We run selected benchmark applications with Critical Bit and other widely used error injection models to demonstrate the differences. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/HPEC.2017.8091090 | 2017 IEEE High Performance Extreme Computing Conference (HPEC) |
Keywords | Field | DocType |
arithmetic operations,floating point arithmetic units,error injection models,voltage-scaled arithmetic units | Architecture,Adder,Computer science,Floating point,Arithmetic | Conference |
ISSN | ISBN | Citations |
2377-6943 | 978-1-5386-3473-8 | 1 |
PageRank | References | Authors |
0.35 | 18 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sungseob Whang | 1 | 1 | 0.68 |
| Tymani Rachford | 2 | 1 | 0.35 |
| Dimitra Papagiannopoulou | 3 | 26 | 3.62 |
| Tali Moreshet | 4 | 98 | 9.81 |
| R. Iris Bahar | 5 | 878 | 84.31 |