Name
Abstract | ||
|---|---|---|
This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Furthermore, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1016/j.microrel.2017.07.007 | Microelectronics Reliability |
Keywords | Field | DocType |
Transient fault,Concurrent error detection,Fault detection,Transient-fault detection | Fault detection and isolation,Combinational logic,Electronic engineering,Engineering,Electronic circuit | Journal |
Volume | ISSN | Citations |
76 | 0026-2714 | 1 |
PageRank | References | Authors |
0.36 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Raphael Andreoni Camponogara Viera | 1 | 5 | 2.24 |
| Rodrigo Possamai Bastos | 2 | 80 | 13.80 |
| Jean-Max Dutertre | 3 | 313 | 29.14 |
| Philippe Maurine | 4 | 276 | 40.44 |
| Rodrigo Iga Jadue | 5 | 1 | 0.70 |