Name
Abstract | ||
|---|---|---|
This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18 mu m standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105 mu mx870 mu m silicon area. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/transele.E101.C.218 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
quick start PLL, phase and frequency presetting | Phase-locked loop,Pulse-width modulation,Optics,Engineering | Journal |
Volume | Issue | ISSN |
E101C | 4 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toru Nakura | 1 | 92 | 31.27 |
| Tsukasa Kagaya | 2 | 0 | 0.68 |
| Tetsuya Iizuka | 3 | 92 | 33.22 |
| kunihiro asada | 4 | 273 | 78.26 |