Name
Title | ||
|---|---|---|
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. |
Abstract | ||
|---|---|---|
An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. ... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/JSSC.2018.2817602 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Frequency modulation,Generators,Calibration,Phase locked loops,Switches | Clock generator,Phase-locked loop,Computer science,Voltage,Electronic engineering,Frequency synthesizer,Digital clock,Frequency modulation,Jitter,Instantaneous phase | Journal |
Volume | Issue | ISSN |
53 | 6 | 0018-9200 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmed Elkholy | 1 | 77 | 16.19 |
| Saurabh Saxena | 2 | 174 | 16.84 |
| Guanghua Shu | 3 | 57 | 9.11 |
| Amr Elshazly | 4 | 242 | 28.08 |
| Pavan Kumar Hanumolu | 5 | 554 | 84.82 |