Name
Abstract | ||
|---|---|---|
In this paper we discuss the potential foundry announced hybrid integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FD-SOI) technology. The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next generation voltage-controlled magnetic anisotropy (VCMA) MTJ are separately integrated into a 28 nm FD-SOI process. Circuit-level design strategies are explored that use FD-SOI leverage and spin-device characteristic to realize writing and reading power-delay efficiency, robust and reliable performance in a 1-transistor 1-MTJ (1T1M) bit cell. Process variation aware strategies for MTJ-FDSOI integration are proposed to compensate failure operations, by using the dynamic step-wise back-bias and the flip-well back-bias. A qualitative summary demonstrates that the MRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISVLSI.2018.00056 | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
MRAM,FDSOI,Bit cell,VCMA MTJ,STT MTJ | Magnetic anisotropy,Computer science,Electronic engineering,CMOS,Magnetoresistive random-access memory,Process variation,Tunnel magnetoresistance,Spin-transfer torque,Transistor,Bit cell | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-5386-7100-9 | 0 |
PageRank | References | Authors |
0.34 | 6 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Cai | 1 | 60 | 21.94 |
| You Wang | 2 | 29 | 9.66 |
| Wang Kang | 3 | 161 | 27.54 |
| Lirida A. B. Naviner | 4 | 83 | 26.52 |
| Xinning Liu | 5 | 8 | 4.02 |
| Jun Yang | 6 | 147 | 36.54 |
| Weisheng Zhao | 7 | 730 | 105.43 |