Name
Title | ||
|---|---|---|
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. |
Abstract | ||
|---|---|---|
The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105mW at a supply voltage of 0.7 V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b at a supply voltage of 0.8 V. The VD, implemented in an exp... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSI.2018.2803735 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Detectors,Decoding,Viterbi algorithm,IEEE 802.3 Standard,EPON,Power demand | Trellis modulation,Intersymbol interference,Pseudorandom binary sequence,Chip,Electronic engineering,CMOS,Decoding methods,Detector,Viterbi algorithm,Mathematics | Journal |
Volume | Issue | ISSN |
65 | 10 | 1549-8328 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
13 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hazar Yueksel | 1 | 7 | 4.15 |
| Matthias Braendli | 2 | 158 | 24.28 |
| A. Burg | 3 | 1426 | 126.54 |
| Giovanni Cherubini | 4 | 52 | 9.18 |
| Roy D. Cideciyan | 5 | 19 | 3.71 |
| Pier Andrea Francese | 6 | 138 | 25.33 |
| Simeon Furrer | 7 | 0 | 1.69 |
| Marcel A. Kossel | 8 | 179 | 33.86 |
| Lukas Kull | 9 | 141 | 18.63 |
| Danny Luu | 10 | 16 | 7.55 |
| Christian Menolfi | 11 | 245 | 41.54 |
| Thomas Morf | 12 | 244 | 42.54 |
| Thomas Toifl | 13 | 275 | 48.02 |