Name
Title | ||
|---|---|---|
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators. |
Abstract | ||
|---|---|---|
PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene. |
Year | Venue | DocType |
|---|---|---|
2018 | VLSI Circuits | Conference |
Volume | Citations | PageRank |
abs/1808.09335 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kentaro Yoshioka | 1 | 54 | 9.04 |
| Yosuke Toyama | 2 | 0 | 0.34 |
| Koichiro Ban | 3 | 43 | 7.32 |
| Daisuke Yashima | 4 | 0 | 0.34 |
| Shigeru Maya | 5 | 0 | 0.34 |
| Akihide Sai | 6 | 20 | 8.25 |
| Kohei Onizuka | 7 | 12 | 3.64 |