Name
Title | ||
|---|---|---|
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing |
Abstract | ||
|---|---|---|
This paper presents a 2-layer 3D stacked Back Side Illuminated vision chip performing high speed programmable parallel computing by exploiting in-focal-plane pixel readout circuits. The proposed circuit exhibits a 5500fps frame rate, 5 times higher than previous works without reducing ADC resolution. It allows heterogeneous parallel computations on up to 31×31 inter-pixels neighborhoods in a single chip. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSIC.2018.8502290 | 2018 IEEE Symposium on VLSI Circuits |
Keywords | Field | DocType |
imager,3D stacking,vision chip | Kernel (linear algebra),Vision chip,Computer science,Cardinal point,Electronic engineering,Chip,Frame rate,Pixel,Electronic circuit,Computer hardware,Image resolution | Conference |
ISSN | ISBN | Citations |
2158-5601 | 978-1-5386-4215-3 | 0 |
PageRank | References | Authors |
0.34 | 0 | 12 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Laurent Millet | 1 | 2 | 1.75 |
| Stéphane Chevobbe | 2 | 29 | 6.50 |
| Caaliph Andriamisaina | 3 | 43 | 4.82 |
| Edith Beigne | 4 | 536 | 52.54 |
| Fabrice Guellec | 5 | 2 | 2.09 |
| Thomas Dombek | 6 | 2 | 1.07 |
| L. Benaissa | 7 | 0 | 0.34 |
| E. Deschaseaux | 8 | 0 | 0.34 |
| M. Duranton | 9 | 0 | 0.34 |
| K. Benchehida | 10 | 0 | 0.34 |
| Mehdi Darouich | 11 | 7 | 2.79 |
| Maria Lepecq | 12 | 0 | 0.34 |