Name
Abstract | ||
|---|---|---|
Parallel computing is a trend to enhance scalability of electronic design automation (EDA) tools using widely available multicore platforms. In order to benefit from parallelism, well-known EDA algorithms have to be reformulated and optimized for multicore implementation. This paper introduces a set of principles to enable a fine-grain parallel AND-inverter graph (AIG) rewriting. It presents a novel method to discover and rewrite in parallel parts of the AIG, without the need for graph partitioning. Experiments show that, when synthesizing large designs composed of millions of AIG nodes, the parallel rewriting on 40 physical cores is up to 36x and 68x faster than ABC commands rewrite −l and drw, respectively, with comparable quality of results in terms of AIG size and depth. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1145/3240765.3240861 | 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
Keywords | Field | DocType |
AND-Inverter Graph,K-Cuts,Logic Rewriting,Parallel Computing,Operator Formulation,Galois System | Boolean function,Logic gate,Computer science,Parallel computing,Real-time computing,Electronic design automation,Rewriting,Graph partition,Multi-core processor,And-inverter graph,Scalability | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-5386-7502-1 | 0 |
PageRank | References | Authors |
0.34 | 18 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinicius Neves Possani | 1 | 11 | 3.04 |
| Yi-Shan Lu | 2 | 14 | 1.07 |
| Alan Mishchenko | 3 | 982 | 84.79 |
| Keshav Pingali | 4 | 3056 | 256.64 |
| Renato P. Ribas | 5 | 204 | 33.52 |
| André Inácio Reis | 6 | 134 | 21.33 |