Parallel Combinational Equivalence Checking | 1 | 0.35 | 2020 |
Unlocking Fine-Grain Parallelism for AIG Rewriting | 0 | 0.34 | 2018 |
Transistor Count Optimization in IG FinFET Network Design. | 0 | 0.34 | 2017 |
Graph-Based Transistor Network Generation Method for Supergate Design | 5 | 0.49 | 2016 |
Exploring Independent Gates in FinFET-Based Transistor Network Generation | 0 | 0.34 | 2014 |
Efficient transistor-level design of CMOS gates | 1 | 0.36 | 2013 |
Improving the methodology to build non-series-parallel transistor arrangements | 2 | 0.41 | 2013 |
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. | 2 | 0.41 | 2012 |