Paper Info
Title
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.
Abstract
Long DRAM access latency is a major bottleneck for system performance. In order to access data in DRAM, a memory controller (1) activates (i.e., opens) a row of DRAM cells in a cell array, (2) restores the charge in the activated cells back to their full level, (3) performs read and write operations to the activated row, and (4) precharges the cell array to prepare for the next activation. The restoration operation is responsible for a large portion (up to 43.6%) of the total DRAM access latency. We find two frequent cases where the restoration operations performed by DRAM do not need to fully restore the charge level of the activated DRAM cells, which we can exploit to reduce the restoration latency. First, DRAM rows are periodically refreshed (i.e., brought back to full charge) to avoid data loss due to charge leakage from the cell. The charge level of a DRAM row that will be refreshed soon needs to be only partially restored, providing just enough charge so that the refresh can correctly detect the cells' data values. Second, the charge level of a DRAM row that will be activated again soon can be only partially restored, providing just enough charge for the activation to correctly detect the data value. However, partial restoration needs to be done carefully: for a row that will be activated again soon, restoring to only the minimum possible charge level can undermine the benefits of complementary mechanisms that reduce the activation time of highly-charged rows. To enable effective latency reduction for both activation and restoration, we propose charge-level-aware look-ahead partial restoration (CAL). CAL consists of two key components. First, CAL accurately predicts the next access time, which is the time between the current restoration operation and the next activation of the same row. Second, CAL uses the predicted next access time and the next refresh time to reduce the restoration time, ensuring that the amount of partial charge restoration is enough to maintain the benefits of reducing the activation time of a highly-charged row. We implement CAL fully in the memory controller, without any changes to the DRAM module. Across a wide variety of applications, we find that CAL improves the average performance of an 8-core system by 14.7%, and reduces average DRAM energy consumption by 11.3%.
Year
DOI
Venue
2018
10.1109/MICRO.2018.00032
MICRO
Keywords
Field
DocType
DRAM-latency,activation-latency,restoration-latency,partial-restoration
Row,Dram,Bottleneck,Access time,Data loss,Computer science,Latency (engineering),Real-time computing,Look-ahead,Computer hardware,Memory controller
Conference
ISBN
Citations 
PageRank 
978-1-5386-6241-0
9
0.39
References 
Authors
30
10
Name
Order
Citations
PageRank
Yaohua Wang14414.23
Arash Tavakkol215110.83
Lois Orosa3224.20
Saugata Ghose471836.45
Nika Mansouri-Ghiasi5181.54
Minesh Patel62049.82
Jeremie Kim726313.68
Hasan Hassan835217.76
Mohammad Sadrosadati9819.33
Onur Mutlu109446357.40