Paper Info
Title
Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS
Abstract
A family of 32b data/64b key SIMON cipher accelerators, each reconfigurable for encrypt/decrypt modes and fabricated in 14nm tri-gate CMOS, is optimized for a range of area and performance targets: (i) a 1080-gate one round/cycle design occupying 136μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area uses reconfigurable circuits for forward/reverse key generation, (ii) a 752-gate 16 cycles/round bit-serial design with a single round/key logic bit-slice lowers layout area by 38% to 85μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and (iii) latch-based key/text storage for the bit-serial circuit reduces area further by 22% to 66μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 272 cycles/round for a 548-gate design with measured 11.4Mbps, 209μW, 750mV operation. Ultra-low voltage circuit optimizations enable peak energy efficiency from 166Gbps/W at 380mV for the bit-serial latch-based design to 12.6Tbps/W at 260mV for the parallel, one round/cycle design.
Year
DOI
Venue
2018
10.1109/ASSCC.2018.8579274
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
Field
DocType
SIMON cipher,ultra-lightweight,encryption,IoT
Cipher,Key generation,Logic gate,Computer science,Efficient energy use,Voltage,Electronic engineering,CMOS,Encryption,Electronic circuit,Electrical engineering
Conference
ISBN
Citations 
PageRank 
978-1-5386-6414-8
0
0.34
References 
Authors
3
8
Name
Order
Citations
PageRank
Himanshu Kaul145651.07
Mark A. Anders218517.43
S. Mathew346276.59
Vikram B. Suresh43110.23
Sudhir Satpathy526919.69
Amit Agarwal669372.95
S. K. Hsu752152.06
Ram Krishnamurthy865074.63