Name
Title | ||
|---|---|---|
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications |
Abstract | ||
|---|---|---|
A small gate count 8 bit bidirectional phase domain MAC (PMAC) circuit is proposed for DNN inference applications targeting IoT edge. PMAC consumes significantly smaller power than standard fully digital MACs, owing to its efficient analog accumulation nature based on Gated-Ring-Oscillator (GRO). Compared with the previous first PoC of PMAC, the bidirectional architecture proposed in this paper achieves 20% less gate count, which is comparable with fully digital MACs, and relaxes system design constraints by eliminating phase error originating in leakage current. Asynchronous readout technique and 2-step DTC for the better system throughput and compact implementation, respectively, are presented for the first time. The PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ASSCC.2018.8579253 | 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | Field | DocType |
DNN accelerator,Phase Domain MAC,GRO | Asynchronous communication,Logic gate,Gate count,PMAC,Leakage (electronics),Computer science,8-bit,Electronic engineering,CMOS,Throughput | Conference |
ISBN | Citations | PageRank |
978-1-5386-6414-8 | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yosuke Toyama | 1 | 0 | 0.34 |
| Kentaro Yoshioka | 2 | 54 | 9.04 |
| Koichiro Ban | 3 | 43 | 7.32 |
| Akihide Sai | 4 | 20 | 8.25 |
| Kohei Onizuka | 5 | 12 | 3.64 |